In system-on-chip (SoC) devices, in which multiple modules of a processing system are integrated onto a single chip, the modules are often required to operate in close synchrony with each other. However, it is also often the case that the different modules of the system operate at different clock rates, with module clocks derived from different physical time bases. The different module clocks will therefore tend to drift relative to one another, and, even when such drift is random, the deviation between any pair of clocks will, on average, increase over time.
In order to provide the needed synchrony among all modules of a SoC device, a global timebase may be created for use as a reference by all of the modules, wherein each module accesses this timebase for real-time measurements. A variety of methods have been developed to provide the timebase to the modules, e.g., by making a global timebase counter register readable by all modules over a data bus or through a system network.
In U.S. patent application publication no. 2004/0117682, Xu describes a system and method for synchronizing the processors of a multiprocessor platform using a globally accessible clock counter. Each processor accesses its own local time value and adjusts its synchronization parametric in time resource structure whereby the local time value is updated.
In U.S. patent application publication no. 2006/0095591, Kelly describes global timing for a cluster of processor nodes, which corrects for internal clock drift among the nodes by including synchronizing pulses from a master clock.
In U.S. patent application publication no. 2007/0016817, Albonesi et al. describe an architecture wherein each functional block operates with a separately generated clock and where synchronizing circuits ensure reliable inter-domain communication. In particular, an externally generated clock is distributed to the local phase lock loop in each domain.
However, existing methods of distributing a global clock signal to the multiple modules or providing access to timebase values in a counter over a data bus tend to incur significant jitter, high latency and overhead.